Quiet Power: Noise Mitigation in Power Planes

Inductive kick has been a well-known phenomenon in the electronics industry from very early on. First associated with motors, AC mains transformers and mechanical relays, people noticed large voltage spikes when the current-carrying circuit was opened. Later, as more sophisticated electronic circuits emerged, the same thing was noticed any time current was changing through an inductor, or for that matter, through any inductance, whether it was an intentionally placed discrete inductor piece or just the parasitic inductance associated with a current path. This phenomenon is captured by the third Maxwell equation, which describes Faraday’s Law1. In its simple form we know this rule from signal integrity as it describes the Dv ground bounce as a function of the dI/dt rate of change of current through an inductance of L:

 Istvan_Oct_Eq1_cap (1).jpg
In today’s electronics, the components are held and connected by printed circuit boards, which have been around for several decades. The front and back side of a small printed circuit board I designed, etched and populated in the late 1960s, are shown in Figure 1.

Istvan_Oct_Fig1_cap.jpg

It was the audio amplifier for a battery-powered portable radio using all germanium transistors. The printed circuit board dielectric was unreinforced, fairly brittle, and to connect all components it was enough to use copper traces only on the back side of the board. The power and ground nets were carried by the wider etches near the two edges of the board. Being an analog audio amplifier using low-frequency transistors with a transit frequency in the order of a megahertz, the circuit did not create high-frequency or high-speed noise, and to carry power around simple traces with no special high-frequency bypassing was sufficient. Though the L inductance of the widely-spaced power and ground traces must have been very high, possibly in the tens of nHs, the noise across it was low because the dI/dt rate of current change was even smaller.

Istvan_Oct_Fig2_cap.jpg
Fast-forward about 50 years; Figure 2 shows the front and back of a CPU module from the late 2010s2. I designed the power distribution network for this board that consumed hundreds of watts, had 20+ layers, and used several hundred bypass capacitors. The board had multiple solid ground layers and multiple power planes for the high-current supply rails. The power and ground planes in close proximity produced very low inductance in the tens of picohenries range, which was necessary to counter the high dI/dt of the chip.

Large power planes provide not only lower inductance, but they are also necessary to keep the DC voltage drop low. However, power planes come with some downsides as they produce resonances that can interfere with both the power delivery, or most likely, with our high-speed signaling. We know that signal traces will resonate if we don’t terminate them properly. Even with proper terminations at the ends, additional reactances along the signaling channel can create quarter-wave or half-wave resonances3. Traces are one-dimensional transmission lines, exhibiting a series of modal resonances associated with their length. Traces are one-dimensional, because we must keep the trace width and dielectric separation much smaller than the shortest wavelength of interest. In contrast, planes are two-dimensional resonators and rectangular plane pairs exhibit modal resonances both along their length and width4,5. As an illustration, Figure 3 shows a simulated impedance surface created by the standing-wave pattern on a 2:1 aspect ratio rectangular plane pair.

Istvan_Oct_Fig3_cap.jpgDepending on the resonance frequencies and the functionality of our circuit on the board, the standing waves and resonances can create issues in any of our major disciplines: signal integrity, power integrity, or electromagnetic compatibility. At locations and frequencies where the impedance is high, a signal via going through the power-ground plane cavity will introduce a dip in the trace’s transfer function (S21), which could be a signal-integrity problem. At the same locations and frequencies, power noise will be higher and if at those frequencies there is sufficient excitation energy from our circuit, the conducted noise can create power integrity issues and the circuit potentially could also radiate enough to create electromagnetic compatibility issues.

If we determine that the resonances could impose a risk to the operation of our circuit, we have a few options to deal with it. One possibility is to push the resonance frequencies high enough that our high-speed signals or power noise from our circuit will not excite them. Since we often use power planes to feed multiple electronic devices on our boards, this possible solution depends on how many devices we need to feed and what are our constraints for their placement. If this mitigation does not work, we must find a way to suppress the modal resonances. One “easy” solution is if the density of our bypass capacitors becomes so high that eventually the cumulative impedance of bypass capacitors become dominant at the resonance frequencies.

While this is a practical possibility and may often happen in very dense and physically small applications, large boards may require too many components to make this a viable option. Another alternative is to use power-ground plane pairs on thin enough laminates that naturally will suppress modal resonances. As it was explained and documented6, the natural attenuation of a power-plane pair increases with decreasing dielectric thickness. With medium and large size boards, a dielectric thickness of 25 mm (1 mil) or less greatly suppresses the resonances. As an illustration, Figure 4 shows measured transfer impedance plots on the same board design manufactured with different dielectric thickness values.

Istvan_Oct_Fig4_cap.jpg
However, laminates thinner than 75 mm (3 mils) come with a price premium, and we also need to consider the usual stackup requirements calling for symmetry. This means we cannot just use one thin laminate layer, we need to use them in pairs in the stackup, even if the circuit would otherwise require only one. Also, in case only a smaller portion of a larger board would require the suppression of plane resonances, we will end up with the same thin laminate horizontally everywhere on the board, also where you don’t really need it. In those applications we can consider another potential solution: terminating the planes7, just as we reduce trace resonances by connecting the proper termination resistance to both ends. Since planes do not have well-defined “ends,” as traces do, we need to connect termination components along their periphery. Power-plane pairs, except for a few special shapes, do not have a specific characteristic impedance and therefore we need to rely on approximations, such as this approximation of a rectangular plane pair with X and Y horizontal dimensions:

Istvan_Oct_Eq2_cap.jpg
Where

Zp is the approximate characteristic impedance of the plane pair in ohms

er is the relative dielectric constant of the laminate

h and P are the laminate thickness and periphery in arbitrary, but identical units

With typical plane sizes and laminate thickness values we use today, the impedance comes out in the tens to hundreds of milliohms range. We need to match this impedance with a number of termination elements, placed around the plane periphery. The number of elements depends on our frequency of interest. We need to make sure that up to the highest frequency of interest, often chosen as the tenth harmonic in the modal resonance series, the phase difference between adjacent termination components is much less than 90 degrees. As a result, we typically end up with a centimeter or so spacing. We then take the P periphery of plane shape and divide by the spacing between adjacent elements and it gives us the N number of terminations. Each termination resistor has to have an N*Zp value; many times it comes out as a few ohms. We also add a small series capacitor in series to each termination resistor to avoid shorting the power-ground plane pair with the termination resistance.

Terminating power planes was an attractive and viable solution a couple of decades ago when computer systems still had a lot of single-ended signaling and fewer supply rails with larger planes. In these days it still could be a viable alternative if system constraints prevent us from placing bypass capacitors to their optimum location. An example of plane termination on a recent computer board in volume production was described in a paper presented at DesignCon in 20218. In this case, the very high density of memory sockets ruled out the placement of bypass capacitors next to the power pins of memory sockets. The simulated and measured impedance of that supply rail is reproduced in Figure 5. Note the logarithmic vertical scale; using the proper termination components, the peak impedance was reduced by at least a factor of two.

Istvan_Oct_Fig5_cap.jpg
Conclusion
Power planes provide a convenient means to connect multiple loads to a single power rail, but they introduce a series of modal resonances. The resonances can be suppressed by many bypass capacitors, or by using sufficiently thin dielectrics or by placing termination components along the plane periphery.

References

  1. For an introductory overview and summary, see for instance, https://byjus.com/physics/maxwells-equations.
  2. “Is Power Integrity the Next Black Magic?” Keynote webinar talk at E-learning By Cadence, April 12, 2021.
  3. “Those Pesky Half-Wave Resonances,” by Gustavo Blando, Signal Integrity Journal, Oct. 19, 2021.
  4. “Microstrip antenna technology,” by K.R. Carver and J.W. Mink, IEEE Transactions on Antennas and Propagation, AP-29, 1981, pp. 2-24.
  5. Frequency Domain Characterization of Power Distribution Networks, Artech House, July 2007, ISBN-13: 978-1-59693-200-5.
  6. “SUN’s Experience with Thin and Ultra-Thin Laminates for Power Distribution Applications,” DesignCon 2006, Santa Clara, CA, Feb. 6–9, 2006.
  7. “Distributed Matched Bypassing for Power Distribution Network,” IEEE Tr. CPMT, August 2002.
  8. “Impact of Power Plane Termination on System Noise,” DesignCon 2021, San Jose, CA, Aug. 16–18, 2021.

This column originally appeared in the October 2022 issue of Design007 Magazine

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2022

Quiet Power: Noise Mitigation in Power Planes

11-07-2022

Inductive kick has been a well-known phenomenon in the electronic industry from very early on. First associated with motors, AC-mains transformers and mechanical relays, people noticed large voltage spikes when the current-carrying circuit was opened. Later as more sophisticated electronic circuits emerged, the same thing was noticed any time when current was changing through an inductor, or for that matter, through any inductance, whether it was an intentionally placed discrete inductor piece or just the parasitic inductance associated with a current path. This phenomenon is captured by the third Maxwell equation, which describes Farady’s Law.

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Quiet Power: Uncompensated DC Drop in Power Distribution Networks

01-19-2022

One recurring question I get is how to factor the DC drop into the power distribution network design process. Whether you prefer time-domain based or frequency-domain based design approach, the DC drop on the distribution path must be taken into account. Professional tools can do a good job to simulate the DC voltage drop on power planes, vias and traces, so after completing the layout, it is always a good idea to check the DC drop to make sure that the design meets the requirements. Here, I will walk you through some of the important options and considerations.

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2021

Quiet Power: Ask the Experts—PDN Filters

07-12-2021

In recent years I have been getting a lot of questions about PDN filters from my course participants and from friends, colleagues and even from strangers. Long gone are the days when the essence of power distribution design recommendation was “place a 0.1uF bypass capacitor next to each power pin.”

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Quiet Power: Friends and Enemies in Power Distribution

04-16-2021

In signal integrity, for high-speed signaling, high-frequency loss is usually considered a bad side effect that we want to minimize. The DC loss, on the other hand, matters much less, because in many high-speed signaling schemes we intentionally block the DC content of the signal.

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2020

Quiet Power: Be Aware of Default Values in Circuit Simulators

08-27-2020

Simulators are very convenient for getting quick answers without lengthy, expensive, and time-consuming measurements. Istvan Novak explains how, sometimes, you can be surprised if you forget about the numerical limits and the limitations imposed by internal default values.

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Quiet Power: Do You Really Need That Ferrite Bead in the PDN?

07-30-2020

Many times, users have to rely on application notes from chip vendors to figure out how to design the PDN for the active device. Within this still vast area of application notes, Istvan Novak focuses on just one question that greatly divides even the experts: Is it okay, necessary, or harmful to use ferrite beads in the PDN?

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Quiet Power: PCB Fixtures for Power Integrity

02-15-2020

Power-integrity components—such as bypass capacitors, inductors, ferrite beads, or other small discrete components—can be characterized in fixtures. Istvan Novak discusses the wide range of PCB fixtures available for power integrity.

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2019

Quiet Power: How Much Signal Do We Lose Due to Reflections?

11-18-2019

We know that in the signal integrity world, reflections are usually bad. In clock networks, reflection glitches may cause multiple and false clock triggering. In medium-speed digital signaling, reflections will reduce noise margin, and in high-speed serializer/deserializer (SerDes) signaling, reflections increase jitter and create vertical eye closure.

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2018

Quiet Power: Measurement-to-Simulation Correlation on Thin Laminate Test Boards

12-19-2018

A year ago, I introduced causal and frequency-dependent simulation program with integrated circuit emphasis (SPICE) grid models for simulating power-ground plane impedance. The idea behind the solution was to calculate the actual R, L, G, and C parameters for each of the plane segments separately at every frequency point, run a single-point AC simulation, and then stitch the data together to get the frequency-dependent AC response. This month, I will demonstrate how that simple model correlates to measured data and simulation results from other tools.

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2017

Quiet Power: Causal Power Plane Models

12-13-2017

Causal and frequency-dependent models and simulations are important for today’s high-speed signal integrity simulations. But are causal models also necessary for power integrity simulations? When we do signal integrity eye diagram simulations, we define the source signals, so if we use the correct causal models for the passive channel, we will get the correct waveforms and eye reduction due to distortions on the main path and noise contributions from the coupling paths. Istvan Novak explains.

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2016

Dynamic Models for Passive Components

05-11-2016

A year ago, my Quiet Power column described the possible large loss of capacitance in multilayer ceramic capacitors (MLCC) when DC bias voltage is applied. However, DC bias effect is not the only way we can lose capacitance. Temperature, aging, and the magnitude of the AC voltage across the ceramic capacitor also can change its capacitance.

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2015

Avoid Overload in Gain-Phase Measurements

07-01-2015

There is a well-established theory to design stable control loops, but in the case of power converters, we face a significant challenge: each application may require a different set of output capacitors coming with our loads. Since the regulation feedback loop goes through our bypass capacitors, our application-dependent set of capacitors now become part of the control feedback loop. Unfortunately, certain combination of output capacitors may cause the converter to become unstable, something we want to avoid. This raises the need to test, measure, or simulate the control-loop stability. Istvan Novak has more.

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Effects of DC Bias on Ceramic Capacitors

04-01-2015

The density of multilayer ceramic capacitors has increased tremendously over the years. While 15 years ago a state-of-the-art X5R 10V 0402 (EIA) size capacitor might have had a maximum capacitance of 0.1 uF, today the same size capacitor may be available with 10 uF capacitance. This huge increase in density unfortunately comes with a very ugly downside. Istvan Novak has more.

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2014

Vertical Resonances in Ceramic Capacitors

12-03-2014

Because of their small size, we might think that structural resonances inside the ceramic capacitors do not exist in the frequency range where we usually care for the PDN. The unexpected fact is that the better PDN we try to make, the higher the chances that structural resonances inside ceramic capacitors do show up. This column tells you why and how.

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Quiet Power: Vertical Resonances in Ceramic Capacitors

12-03-2014

Because of their small size, we might think that structural resonances inside the ceramic capacitors do not exist in the frequency range where we usually care for the PDN. The unexpected fact is that the better PDN we try to make, the higher the chances that structural resonances inside ceramic capacitors do show up. This column tells you why and how.

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Checking Cable Performance with VNA

04-02-2014

In a previous column, Columnist Istvan Novak showed that poor cable shields can result in significant noise pickup from the air, which can easily mask a few mV of noise voltage needed to measure on a good power distribution rail. In this column, he looks at the same cables in the frequency domain, using a pocket-size vector network analyzer (VNA).

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Quiet Power: Checking Cable Performance with VNA

04-02-2014

In a previous column, Columnist Istvan Novak showed that poor cable shields can result in significant noise pickup from the air, which can easily mask a few mV of noise voltage needed to measure on a good power distribution rail. In this column, he looks at the same cables in the frequency domain, using a pocket-size vector network analyzer (VNA).

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Comparing Cable Shields

01-08-2014

In his last column, Istvan Novak looked at the importance of properly terminating cables even at low frequencies and also showed how much detail can be lost in PDN measurements when bad-quality cables are used. This month, he analyzes a step further the shield in cables.

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2013

Quiet Power: Cable Quality Matters

11-20-2013

In his August column Istvan Novak looked at the importance of properly terminating the cables that connect a measuring instrument to a device under test. He writes that we may be surprised to learn that even if the correct termination is used at the end of the cable, the measured waveform may depend on the quality of the cable used.

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Quiet Power: Don't Forget to Terminate Cables

10-23-2013

In high-speed signal integrity measurements, the first rule is to properly terminate traces and cables. However, many PDN measurements may be limited to lower frequencies, such as measuring the switching ripple of a DC-DC converter. Do you really need to terminate measurement cables if the signal you want to measure is the switching ripple of a converter running at 1 MHz?

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Quiet Power: Do Not Measure PDN Noise Across Capacitors!

08-07-2013

PDN noise can be measured in a variety of ways, but measuring across a capacitor will attenuate the high-frequency burst noise. Keep in mind that by measuring across a capacitor, the converter output ripple reading could be several times higher--or many times smaller--than the actual ripple across our loads.

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Quiet Power: How to Read the ESR Curve

01-15-2013

To use bypass capacitors properly, any designer must understand ESR (effective series resistance). A designer must understand what it means and how to read the ESR curve in measured or simulated plots.

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2012

Quiet Power: What's the Best Method for Probing a PDN?

08-15-2012

Recently, one of Istvan Novak's friends asked him about the preferred method of probing a power distribution network: "Which probe should I use to measure power plane noise?" Although, as usual, the correct answer begins with "It depends," in this case the generic answer is more clear-cut: For many PDN measurements, a simple passive coaxial cable is better.

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Quiet Power: Will Power Planes Disappear?

04-04-2012

Istvan Novak takes a look at an award-winning paper presented at DesignCon 2012, and he discusses the apparent disappearance of power planes from PCBs. In the future, the need for power planes may diminish or go away altogether. The change is already under way, and power planes, full-layer planes in particular, are disappearing fast from printed circuit boards.

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Do Bypass Capacitors Change Plane Resonances?

02-01-2012

My friend Greg recently asked me, "If I add surface-mount capacitors to a bare pair of planes, I am told that the resonant frequency will drop. On the other hand, someone with expertise is telling me that this is not the case. What would you expect to see?" As happens many times, both observations have elements of the truth in them, and a third scenario is not out of the question.

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2011

Be Careful with Transmission Lines in Plane Models

11-16-2011

Last month, we learned how we can determine the grid equivalent circuit parameters for a plane pair. You may wonder: Is it better to use LC lumped components in the SPICE netlist or to make use of SPICE's built-in transmission line models? In short, we can use either of them, but we need to set up our models and expectations correctly.

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Quiet Power: Simulating Planes with SPICE

10-12-2011

There are several excellent commercial tools available for simulating power distribution planes. However, you don't need a commercial tool to do simple plane analysis. You can, for instance, write your SPICE input file and use the free Berkeley SPICE engine to get result. If you want to do your own plane simulations, there are a couple of simple choice.

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Quiet Power: Does Dk Matter for Power Distribution?

08-16-2011

We know that in signal integrity, the relative dielectric constant (Dk) of the laminate is important. Dk sets the delay of traces, the characteristic impedance of interconnects and also scales the static capacitance of structures. Is the same true for power distribution? The answer is yes, but for power distribution all this matters much less.

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2010

Do Not Perforate Planes Unnecessarily

11-03-2010

For this column, I will take a quick detour from the series on the inductance of bypass capacitors. I will devote this column to a few comments about via placement and its potentially detrimental impact on signal and power integrity when antipads heavily perforate planes.

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Inductance of Bypass Capacitors, Part III

08-18-2010

In Part III of a series, we'll take a look at loop or mounted inductance. Loop inductance is important, for instance, when we need a reasonably accurate estimate for the Series Resonance Frequency (SRF), or for the anti-resonance peaking between two different-valued capacitors or between the capacitor's inductance and the static capacitance of the power/ground planes it connects to.

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Quiet Power: Inductance of Bypass Capacitors, Part II

07-21-2010

We finished the last Quiet Power column with a few questions about the inductance of bypass capacitors: Why do different vendors sometimes report different inductance values for nominally the same capacitor? Start by asking the vendors how they obtained these inductance values.

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Why PI Design is More Difficult Than SI

05-19-2010

Why is power integrity design more difficult than signal integrity design? Reasons abound, and unlike SI, we've only begun to study PI. Collective wisdom and experience gained over the coming years will help to alleviate the pain somewhat, but we should expect the challenge to stay with us for some time.

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Why S11 VNA Measurements Don't Work for PDN Measurements

04-14-2010

In this edition of Quiet Power, Istvan Novak continues to examine one-port and two-port vector network analyzer set-ups for PDN measurements, and other tricks and techniques for measuring impedance values below 5 milliohms.

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PDN Measurements: Reducing Cable-Braid Loop Error

02-24-2010

At low and mid frequencies, where the self-impedance of a DUT may reach milliohm values, a fundamental challenge in measurement is the connection to the DUT. Unless we measure a single component in a well-constructed fixture, the homemade connections from the instrument to the DUT will introduce too much error. What's the solution? By Istvan Novak.

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Quiet Power: Calculating Basic Resonances in the PDN

01-27-2010

In my last column, I showed that the piecewise linear Bode plots of various PDN components can create peaking at some interim frequencies. Today, I must cover peaking in more detail, because, even today, certain articles, books and CAD tools provide the wrong answers to this problem.

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